1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of reducing gate leakage in semiconductor devices such as transistors.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped source/drain regions. The channel length of a MOS transistor is generally considered to be the lateral distance between the source/drain regions.
FIGS. 1A-1C depict portions of an illustrative process flow for forming the gate structure of an illustrative prior art transistor device 100. The process typically begins with the formation of an illustrative trench isolation structure 12 in a semiconducting substrate 10. The isolation structure 12 defines an active area in the substrate 10 where the transistor 100 will be formed. The basic gate formation process begins with the formation of multiple layers of material above the substrate 10. In the depicted example, a gate insulation layer 14 (e.g., silicon dioxide), a layer of gate electrode material 16 (e.g., polysilicon) and a gate capping material layer 18 (e.g., silicon nitride) are formed above the substrate 10 using known processing techniques. Thereafter, with reference to FIG. 1B, a patterned masking layer (not shown), such as a photoresist mask, is formed above the gate capping layer 18 and one or more etching processes are performed through the patterned mask layer to define a gate insulation layer 14A, a gate electrode 16A and a gate cap 18A, as depicted in FIG. 1B. Next, as shown in FIG. 1C, a relatively high temperature (about 950° C.) gate re-oxidation process is performed that results in the formation of an illustrative layer of silicon dioxide 20. An illustrative source region 22S and drain region 22D are also formed in the substrate 10 by using known ion implantation tools and techniques. Of course, as will be appreciated by those skilled in the art, there are numerous additional steps that need to be performed to complete the fabrication of the illustrative transistor 100, e.g., the formation of so-called halo implant regions in the substrate 10, the formation of one or more sidewall spacers proximate the gate electrode 16A, the formation of various conductive contacts to establish electrical connection to the device 100, etc.
Depending upon the operation conditions, i.e., whether the transistor 100 is turned “ON” or “OFF,” there will be undesirable leakage current between the gate electrode 16A and one or both of the illustrative source/drain regions 22S, 22D formed in the substrate 10. This gate leakage current can be separated into two different categories—an area leakage component and a boundary leakage component. The area leakage component is based upon the contact area between the gate insulation layer 14A and the surface of the substrate 10. To reduce the gate leakage current due to this area leakage component, device designers have taken several actions, such as using so-called high-k (k value greater than 10) insulating materials for the gate insulation layer 14A.
The boundary leakage component occurs at the edges 14E of the gate insulation layer 14A around the perimeter of the gate insulation layer 14A, particularly along the edges 14E that extend in the gate width direction (i.e., into the drawing page shown in FIG. 1C). When the transistor 100 is “OFF,” gate boundary leakage occurs between the gate electrode 16A and the drain region 22D; when the transistor 100 is “ON,” gate boundary leakage occurs between the gate electrode 16A and both the source region 22S and the drain region 22D. The act of patterning the gate insulation layer 14A and the gate electrode 16A results in a damaged region 14D proximate the etched edges 14E of the gate insulation layer 14A, as depicted in the enlarged insert shown in FIG. 1C. This relatively vertically-oriented damaged region 14D consists of unsaturated and dangling bonds which create a two-dimensional density of states that provides an electrical conduction path for current flow between the gate electrode 16A and the source/drain regions 22S, 22D. Traditionally, device designers have performed the previously described, relatively high temperature (about 950° C.) gate re-oxidation process in an effort to re-crystallize the damaged region 14D to try to reduce the boundary component of the gate leakage current. However, modern transistor devices typically do not have sufficient “thermal budget” to allow for such a high temperature re-oxidation process to be performed. Accordingly, the boundary component of the gate leakage current is becoming more problematic in modern, high-performance transistor devices.
The present disclosure is directed to various methods of reducing gate leakage in semiconductor devices such as transistors that may avoid, or at least reduce, the effects of one or more of the problems identified above.